Report 471

 Report 471 Essay

LAB you REPORT -- Free-E CSE471

Design a MIPS thirty-two by thirty-two Register Record

Group six: 1 . Le Minh Hoang 2 . Votre Hong Thang 3. Luong Tran Nhat Trung

Prof. Ho Viet Viet LA: Nguyen Van Hieu

Report Lab 1 – Group 6 – EE471- 09ECE

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Table of content:

пЃ¶ пЃ¶ пЃ¶ пЃ¶ пЃ¶ пЃ¶ пЃ¶ пЃ¶

Summary Block Diagram Decoder component Multiplexor component Register module Regfile component Simulation result Trade-off

Survey Lab 1 – Group 6 – EE471- 09ECE

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ABSTRACT:

The goal of this design and style problem is to design a 32x32 register data file that can compose data in and go through 2 ports data simultaneously. The value of each register in the register document remains unrevised until the following write transmission is allowed and the write data is available.

BLOCK PLAN:

+ Decoder block: decoding the 5-bit signal via Write Sign-up to choose which in turn register is used to write the info. This block only works when the signal via RegWrite is usually sent to switch on the prevent. + You will discover 32 signup from zero to 31, the enroll 0 contains only little 0 while default. The data signal by WriteData will be sent to the chosen enroll from the decoder block.

Record Lab you – Group 6 – EE471- 09ECE

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+ Every bit coming from 32 register will send towards the Multiplexor prevent and, this kind of block will receive 32 portions from every single register everytime. + The Read Sign-up 1 and 2 can choose which bit coming from 32 register will be read out in Browse Data 1 and two from the Multiplexor block. + 32 register are designed from your DFF, every single register features 32 bits, each tad is 1 DFF

DECODIERER:

+ 5-bit input and 32-bit output + Solving to choose which usually register will probably be written WR[0] 0 zero 0 zero 0 0... 1 you WR[1] 0 0 0 0 zero 0... you 1 WR[2] 0 0 0 0 1 1 ... 1 you WR[3] 0 0 one particular 1 0 0... one particular 1 WR[4] 0 one particular 0 1 0 1 ).. 0 one particular WE[0] 1 0 0 0 zero 0... 0 0 WE ALL[1] 0 you 0 zero 0 0... 0 0 WE[2] zero 0 one particular 0 0 0... zero 0 ALL OF US[3] 0 0 0 one particular 0 zero... 0 0 WE[4] zero 0 zero 0 1 0... zero 0 WE ALL[5] 0 zero 0 0 0 1 ).. 0 zero.............................. WE[30] zero 0 zero 0 zero 0... 1 0 ALL OF US[31] 0 zero 0 zero 0 0... 0 one particular

The true table of the decoder:

Code:

component decoder(WE, RegWrite, WR); end result [31: 0] WE; insight [4: 0] WR;

type RegWrite; cable notWR0, notWR1, notWR2, notWR3, notWR4; line And01, And23, And45, And67, And89, And1011, And1213, And1415, And1617, And1819, And2021, And2223, And2425, And262 7, And2829, And3031;

not really #(50) Inv0( notWR0, WR[0]); not #(50) Inv1( notWR1, WR[1]); not #(50) Inv2( notWR2, WR[2]);

Report Research laboratory 1 – Group six – EE471- 09ECE

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not #(50) Inv3( notWR3, WR[3]); not #(50) Inv4( notWR4, WR[4]);

and #(50) And1 ( And01 and #(50) And2 ( And23 and #(50) And3 ( And45 and #(50) And4 ( And67 and #(50) And5 ( And89

, notWR4, notWR3, notWR2, notWR1);, notWR4, notWR3, notWR2, WR[1] );, notWR4, notWR3, WR[2]#@@#@!!, notWR1);, notWR4, notWR3, WR[2]#@@#@!!, WR[1] );, notWR4, WR[3]#@@#@!!, notWR2, notWR1);

and #(50) And6 ( And1011, notWR4, WR[3]#@@#@!!, notWR2, WR[1] ); and #(50) And7 ( And1213, notWR4, WR[3]#@@#@!!, WR[2]#@@#@!!, notWR1); and #(50) And8 ( And1415, notWR4, WR[3]#@@#@!!, WR[2]#@@#@!!, WR[1] ); and #(50) And9 ( And1617, WR[4]#@@#@!!, notWR3, notWR2, notWR1); and #(50) And10( And1819, WR[4]#@@#@!!, notWR3, notWR2, WR[1] ); and #(50) And11( And2021, WR[4]#@@#@!!, notWR3, WR[2]#@@#@!!, notWR1); and #(50) And12( And2223, WR[4]#@@#@!!, notWR3, WR[2]#@@#@!!, WR[1] ); and #(50) And13( And2425, WR[4]#@@#@!!, WR[3]#@@#@!!, notWR2, notWR1); and #(50) And14( And2627, WR[4]#@@#@!!, WR[3]#@@#@!!, notWR2, WR[1] ); and #(50) And15( And2829, WR[4]#@@#@!!, WR[3]#@@#@!!, WR[2]#@@#@!!, notWR1); and #(50) And16( And3031, WR[4]#@@#@!!, WR[3]#@@#@!!, WR[2]#@@#@!!, WR[1] );

and #(50) WE0 ( WE[0]#@@#@!!, RegWrite, And01 and #(50) WE1 ( WE[1]#@@#@!!, RegWrite, And01 and #(50) WE2 ( WE[2]#@@#@!!, RegWrite, And23 and #(50) WE3 ( WE[3]#@@#@!!, RegWrite, And23 and #(50) WE4 ( WE[4]#@@#@!!, RegWrite, And45 and #(50) WE5 ( WE[5]#@@#@!!, RegWrite, And45 and #(50) WE6 ( WE[6]#@@#@!!, RegWrite, And67 and #(50) WE7 ( ALL OF US[7]#@@#@!!, RegWrite, And67 and #(50) WE8 ( WE[8]#@@#@!!, RegWrite, And89 and #(50) WE9 ( ALL OF US[9]#@@#@!!, RegWrite, And89

, notWR0 );, WR[0] );

, notWR0 );, WR[0] );

, notWR0 );, WR[0] );

, notWR0 );, WR[0] );

, notWR0 );, WR[0] );

and #(50)...

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